FIN FET - part 2

Why Fin FET ?

The solution of the Vth leakage is create a new architecture whereby it is fully depleted devices for better short - channel control.

Fully depleted channel -> Steeper slope -> Target lower threshold voltage -> improve circuit speed

GATE DELAY :

 Circuits slow down as Vdd reduces

 Planar improves over previous node

  FinFET improves over planar, particular at low Vdd

                    FinFET can operate at lower Vdd, reducing active power >50%

FIN FET :

▸ Enables low Vdd operation and chip power savings

▸ Expected to be adopted as mainstream at 16-14nm

Challenges are in process control

▸ Wfin, Hfin

▸ Gate profile

▸ Junction, Strain...

Outlook 11-10nm and beyond ?

▸ FinFET using non-Si channels...SiGe, IIIV

Resource :

S. Biesemans, VP Process Technology & Strategy, FINFET FOR SUB-22NM TECHNOLOGY NODES